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JPEG » DOS » MSDOS » VBDOS » CppDataType » CppFileIo » server » CppStreamInOperator » CppStreamOutOperator » PCI BUS
Displaying differences between revision 10 and the latest revision
[purple] [size=4] [b] ALL ABOUT PCI LOCAL BUS [/b] [/size] [/purple][br]
[br]
The PCI (Peripheral Component Interconnect) is a high performance Bus for interconnecting chips, expansion boards, and memory cards. It was originated at Intel Inc. In the early 1990’s as standard methods of interconnecting chips on a board. It was later adopted as an industry standard administered by the[[PCI]] Special Interest Group or the PCI SIG.
[purple] [size=2] [b] History: [/b] [/size] [/purple][br]
It was first adopted for use in personal computers in about 1994 with Intel’s introduction of the chip named ?Saturn for the 486 microprocessor. With the introduction of chips and motherboards,[[PCI]] began to replace the then industry standard ISA </b></strike></font>bus<font color=red><strike><b>.
On September 11, 1998 the Special Interest Group formed of Compaq, Hewlett-Packard and IBM had submitted a new specification for review called PCI-X. The proposed standard allows for increase in[[PCI]] [[Bus | bus]] speeds to 133 MHz. [br]
[purple] [size=2] [b] The[[Bus]]: [/b] [/size] [/purple][br]
The basic form of the[[PCI]] presents a fusion of sorts between [[ISA]] and VL-Bus. It provides direct access to system memory for connected devices, but uses a ?bridge to connect to the frontside [[bus]] and therefore to the CPU. Basically, this means that it is capable of even higher performance than [[VL-Bus]] while eliminating the potential for interference with the [[CPU]]. [[PCI]] can connect more devices than [[VL-Bus]], up to five external components. Each of the five connectors for an external component can be replaced with two fixed </b></strike></font>devices<font color=red><strike><b> on the [[motherboard]]. Also, you can have more than one [[PCI]] [[bus]] on the same computer, although this is rarely done. The [[PCI]] [[bridge]] chip regulates the speed of the [[PCI]] [[bus]] independently of the [[CPU]]'s speed. This provides a higher degree of reliability and ensures that [[PCI]] hardware manufacturers know exactly what to design for.[br]
[[PCI]] originally operated at 33 [[MHz]] using a 32-bit-wide path. Revisions to the standard include increasing the speed from 33 [[MHz]] to 66 [[MHz]] and doubling the [[bit]] count to 64. Currently, [[PCI-X]] provides for 64-[[bit]] transfers at a speed of 133 [[MHz]] for an amazing 1-Gbps (gigabit per second) transfer rate. [br]
[br][[¶
PCI]] cards use 47 pins to connect provided there is a [[CPU]]. The [[PCI]] [[bus]] is able to work with so few pins because of hardware ?multiplexing, which means that the [[device]] sends more than one signal over a single pin.. The connectors at the end of the card are connected to the [[motherboard]] slot and are called gold fingers.[br]
[br]Although Intel proposed the[[PCI]] standard in 1991, it did not achieve popularity until the arrival of Windows 95 (in 1995). This sudden interest in [[PCI]] was due to the fact that [[Windows]] 95 supported a feature called Plug and Play ([[PnP]]). [[PCI]] supports devices that use either 5 volts or 3.3 volts.
[purple] [size=2] [b][[PCI]] [[Bus]] Performance[/b] [/size] [/purple][br]
The[[PCI]] [[bus]] provides superior performance to the VESA local [[bus]]; in fact, [[PCI]] is the highest performance general I/O [[bus]] currently used on PCs. This is due to several factors: [br]
* [purple] [size=2] [b] [[burst | Burst]] Mode: [/b] [/size] [/purple][br] The[[PCI]] [[bus]] can transfer information in a [[burst mode]], where after an initial address is provided multiple sets of data can be transmitted in a row. This works in a way similar to how cache </b></strike></font>bursting<font color=red><strike><b> works. [br]
* [purple] [size=2] [b][[Bus]] Mastering: [/b] [/size] [/purple][br] PCI supports full bus mastering, which leads to improved performance. [br]
* [purple] [size=2] [b] High Bandwidth Options: [/b] [/size] [/purple][br] The[[PCI]] [[bus]] specification 2.1 calls for expandability to 64 </b></strike></font>bits<font color=red><strike><b> and 66 [[MHz]] speed; if implemented this would quadruple bandwidth over the current design. In practice the 64-[[bit]] [[PCI]] [[bus]] has yet to be implemented on the PC (it does exist in non-PC platforms such as Digital Equipment's Alpha and is also found now on servers) and the speed is currently limited to 33 [[MHz]] in most PC designs, most likely for compatibility reasons.[br]
* [purple] [size=2] [b] The Speed of the[[PCI]] [[bus]][/b] [/size] [/purple][br] can be set [[Ssynchronous | synchronously]] or [[Aasynchronous | asynchronously]], depending on the chipset and [[motherboard]]. In a ?</b></strike></font>synchronized<font color=red><strike><b> setup (used by most PCs), the [[PCI]] [[bus]] runs at half the [[memory]] [[bus]] speed; since the [[memory]] [[bus]] is usually 50, 60 or 66 [[MHz]], the [[PCI]] [[bus]] would run at 25, 30 or 33 [[MHz], respectively. In an [[asynchronous]] setup, the speed of the [[PCI]] [[bus]] can be set independently of the [[memory]] [[bus]] speed. This is normally controlled through jumpers on the [[motherboard]], or BIOS settings. Overclocking the system [[bus]] on a PC that uses [[synchronous]] [[PCI]] will cause [[PCI]] peripherals to be </b></strike></font>overclocked<font color=red><strike><b> as well, often leading to system stability problems.[br]
The[[PCI-X]] 2.0 specification defines two new versions of [[PCI-X]] add-in cards: [[PCI-X]] 266 and [[PCI-X]] 533.[br]
[[PCI-X]] 266, runs at speeds up to 266 Mega transfers per second, enabling sustainable [[PCI]] bandwidth of more than 2.1 Gigabytes/second. [br]
[[PCI-X]] 533 runs at speeds up to 533 Mega transfers per second enabling bandwidth of more than 4.2 Gigabytes/second.
[purple] [size=2] [b][[PCI]] Technical information [/b] [/size] [/purple][br]
[[PCI]] is basically a 5 [[volt]], 33[[MHz]], 32-[[bit]] bus with a basic data transfer rate of 133 Mb/s. [br]
[[PCI]] also has many design options which can be combined in any permutation.:
* 64-[[bit]] [[bus]] extension - basic data transfer rate of 266Mb/s
* 66-[[MHz]] extension - doubles basic data transfer rate.
* 3.3v operation - via a different physical connector.
* "MiniPCI" connector for laptops and PDA’s
[purple] [size=2] [b] Physical Connector [/b] [/size] [/purple][br]
Most readers should be familiar with the connector variation pictured above - this is the 'standard'[[PCI]] slot found in most x86 [[IBM]] PC clones. This connector represents the most basic [[PCI]] implementation - 32 [[bit]], 33[[MHz]], 5 volt. The 3.3 volt implementation looks the same, except the plastic polarization key is located at the 'top' end, rather than the 'bottom' end. [br]
The 64-[[bit]] implementation are about 50% longer; a second connector is butted up against the end of the standard connector, with the plastic ends of the two connectors forming a second polarization key. The 64-[[bit]] extension always operates at 3.3 volts. Some </b></strike></font>motherboard<font color=red><strike><b>s erroneously label the 64-[[bit]] extension as a 'Media' connector.[br]
[[PCI]] Cards are the 'mirror' of traditional [[IBM]]-PC [[ISA]] [[bus]] cards; that is the components are fitted on the opposite side of the card. The [[PCI]] connector aligns with the right hand edge of the expansion slot, whereas [[ISA]] connects align with the left hand edge. This means that </b></strike></font>motherboards<font color=red><strike><b> can be designed with a 'shared' slot - if the [[ISA]] and [[PCI]] connectors are placed side by side, either an [[ISA]] card, OR a [[PCI]] card can be fitted, but not both at the same time. This is often done to save space on a motherboard, yet try to offer the end user as much flexibility as possible to fit whatever selection of cards the user may have in mind.[br]
Each[[PCI]] ?slot consists of a ?</b></strike></font>multiplex<font color=red><strike><b>ed [[address]] and data [[bus]], four interrupt lines, +5v, +3.3v +12v and -12v power supply lines, card presence sensing, test and control lines. [[PCI]] does not support [[DMA]] in the 'traditional' [[IBM]]-PC sense, however [[bus mastering]] replaces the hold up, utilizing the functionality of [[DMA]] when required.[br]
[[PCI]] sports a number of improvements rarely found in earlier system expansion [[bus]] designs:[br]
* [purple] [size=2] [b] Jumperless Configuration: [/b] [/size] [/purple][br]
*</b></strike></font>devices<font color=red><strike><b> are configured by software means only (A few lazy, stupid vendors do break the rules, though). All </b></strike></font>devices<font color=red><strike><b> are required to report in unambiguous terms their system ?resource requirements:
*[[Memory]] ranges
* I/O addresses
*[[DMA]] channels
* Interrupts
* etc
* [purple] [size=2] [b][[Device]] Identification: [/b] [/size] [/purple][br]
*</b></strike></font>devices<font color=red><strike><b> must identify themselves by their assigned manufacturer and [[device]] codes, as well as reporting their class codes.
* Manufacturer codes are administered by a central authority - the[[PCI]] [[SIG]].
* Class codes aim to provide a basic identification of a[[device]], so that 'generic' system driver software can form some basic understanding and even provide basic control of the [[device]] (in the absence of [[device]]-specific [[driver]] software).
* [purple] [size=2] [b] Platform Independence: [/b] [/size] [/purple][br]
*[[PCI]] can be implemented on almost any computing platform, not just the [[IBM]]-PC/x86 architecture. Many non-PC vendors are adopting [[PCI]], Apple and SUN for instance.
[purple] [size=4] [b] Mini[[PCI]][/b] [/size] [/purple][br]
The Mini[[PCI]] specification defines an alternate implementation for small form factor [[PCI]] cards referred to in this specification as a Mini [[PCI]] card. This specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the Conventional [[PCI]] Specification. Where this specification does not explicitly define [[PCI]] characteristics, the Conventional [[PCI]] specification governs.[br]
The primary differences are:
* The form factor of the card and card and slot connections, that is, the smaller physical size of the Mini[[PCI]] card and the connectors it uses.
* Support of the CLKRUN# signal defined in the[[PCI]] Mobile Design Guide
* No support for optional JTAG signals
* The use of standard sideband signals for audio and communications
* No support for the 64-[[bit]] [[PCI]] extension defined in Conventional [[PCI]]
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JPEG » DOS » MSDOS » VBDOS » CppDataType » CppFileIo » server » CppStreamInOperator » CppStreamOutOperator » PCI BUS
Displaying differences between revision 10 and the latest revision
[purple] [size=4] [b] ALL ABOUT PCI LOCAL BUS [/b] [/size] [/purple][br]
[br]
The PCI (Peripheral Component Interconnect) is a high performance Bus for interconnecting chips, expansion boards, and memory cards. It was originated at Intel Inc. In the early 1990’s as standard methods of interconnecting chips on a board. It was later adopted as an industry standard administered by the
[purple] [size=2] [b] History: [/b] [/size] [/purple][br]
It was first adopted for use in personal computers in about 1994 with Intel’s introduction of the chip named ?Saturn for the 486 microprocessor. With the introduction of chips and motherboards,
On September 11, 1998 the Special Interest Group formed of Compaq, Hewlett-Packard and IBM had submitted a new specification for review called PCI-X. The proposed standard allows for increase in
[purple] [size=2] [b] The
The basic form of the
PCI
[br]Although Intel proposed the
[purple] [size=2] [b]
The
* [purple] [size=2] [b] [[burst | Burst]] Mode: [/b] [/size] [/purple][br] The
* [purple] [size=2] [b]
* [purple] [size=2] [b] High Bandwidth Options: [/b] [/size] [/purple][br] The
* [purple] [size=2] [b] The Speed of the
The
[purple] [size=2] [b]
* 64-
* 66-
* 3.3v operation - via a different physical connector.
* "MiniPCI" connector for laptops and PDA’s
[purple] [size=2] [b] Physical Connector [/b] [/size] [/purple][br]
Most readers should be familiar with the connector variation pictured above - this is the 'standard'
The 64-
Each
* [purple] [size=2] [b] Jumperless Configuration: [/b] [/size] [/purple][br]
*
*
* I/O addresses
*
* Interrupts
* etc
* [purple] [size=2] [b]
*
* Manufacturer codes are administered by a central authority - the
* Class codes aim to provide a basic identification of a
* [purple] [size=2] [b] Platform Independence: [/b] [/size] [/purple][br]
*
[purple] [size=4] [b] Mini
The Mini
The primary differences are:
* The form factor of the card and card and slot connections, that is, the smaller physical size of the Mini
* Support of the CLKRUN# signal defined in the
* No support for optional JTAG signals
* The use of standard sideband signals for audio and communications
* No support for the 64-
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